Impact of Test Compression on Power Supply Noise Control Conference Paper

abstract

• 2015 IEEE. Compaction and compression are commonly used to minimize test data volume and test application time. Both techniques can greatly affect power supply noise (PSN) during test, as these techniques take advantage of the fact that test patterns have low care-bit density. However, there is little prior work studying how compression affects PSN. In this work, embedded deterministic test (EDT) and Illinois Scan patterns are generated with and without compaction. Our previous PSN control algorithm is extended to incorporate the compression constraints and applied to these patterns. The experimental results show that with the PSN control algorithm, EDT lowers the maximal PSN by 24.15% and Illinois Scan lowers it by 2.77% on un-compacted patterns. The maximal PSN is 22.32% and 6.94% lower on compacted patterns.

name of conference

• 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)

authors

• Walker, Duncan

published proceedings

• 2015 IEEE International Symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems (DFTS)
• PROCEEDINGS OF THE 2015 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI AND NANOTECHNOLOGY SYSTEMS (DFTS)

author list (cited authors)

• Zhang, T., & Walker, D.

citation count

• 0

complete list of authors

• Zhang, Tengteng||Walker, DMH

publication date

• October 2015

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems  Journal

keywords

• Power Supply Noise
• Test Compaction Compression

Digital Object Identifier (DOI)

• 10.1109/dft.2015.7315155

International Standard Book Number (ISBN) 13

• 9781509003129

start page

• 161

end page

• 166

URL

• http://dx.doi.org/10.1109/dft.2015.7315155