A fast algorithm for critical path tracing in VLSI digital circuits Conference Paper

abstract

• An exact, linear-time critical path tracing algorithm is presented The performance of critical path tracing is determined primarily by the efficiency of stem analysis. The proposed strategy can determine stem criticality in one pass based on six rules. Experiments on ISCAS85 and ISCAS89 benchmark circuits show that the computation time is nearly linear in the number of nets. 2005 IEEE.

name of conference

• 20th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT'05)

authors

• Walker, Duncan

published proceedings

• DFT 2005: 20TH IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS

author list (cited authors)

• Wu, L., & Walker, D.

citation count

• 23

complete list of authors

• Wu, L||Walker, DMH

publication date

• January 2005

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems  Journal

keywords

• 40 Engineering
• 4008 Electrical Engineering
• Stem Cell Research
• Stem Cell Research - Nonembryonic - Non-human

Digital Object Identifier (DOI)

• 10.1109/DFTVS.2005.6

International Standard Book Number (ISBN) 10

• 0-7695-2464-8

start page

• 178

end page

• 186

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fdftvs.2005.6