Chip level power supply partitioning for IDDQ testing using built-in current sensors Conference Paper

abstract

• 2003 IEEE. The International Technology Roadmap for Semiconductors projects that IDDQ levels will rise rapidly with each technology node. In addition, manufacturing variations in the IDDQ level will be difficult to control. The combination will make it increasingly difficult to distinguish defect-free from defective chips via IDDQ tests. Built-in current sensors (BICSs) have been proposed to increase test resolution by virtually partitioning the supply mesh, so that each partition has a relatively small defect-free IDDQ level. In the future such a scheme would require 100 000 or more BICSs and thus the partitioning task needs to be automated. This paper presents a practical methodology to do this power supply partitioning.

authors

• Walker, Duncan

published proceedings

• Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

author list (cited authors)

• Prasad, A., & Walker, D.

complete list of authors

• Prasad, A||Walker, DMH

publication date

• January 2003

published in

• Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems  Journal

Digital Object Identifier (DOI)

• 10.1109/TSM.2005.1250105

International Standard Book Number (ISBN) 10

• 0769520421

start page

• 140

end page

• 147

volume

• 2003-January