Circuit-level modeling of spot defects
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abstract
1991 IEEE. This paper describes some of the problems faced in mapping spot defects (e.g. extra/missing material, gate oxide pinholes) to changes in the nominal circuit. Traditionally, a very simple mapping has been used, with circuit faults assumed to consist of shorts, opens and occasionally, extra devices. We discuss some of the problems in achieving the simple mapping and how they are solved in VLASIC catastrophic fault yield simulator. We also describe modeling problems that appear to require full 3-D device simulation. Finally some investigations into the hazy boundary between parametric and functional faults are described In this article, we introduce some of the problems faced in mapping spot defects to changes in the nominal circuit. We consider extra or missing material defects and gate oxide pinholes that alter the topology of the circuit only. Device parameter variations due to the defects, though important, are ignored. It is important to model these defects accurately for several reasons. First, good models help evaluate testing schemes. Since these models transfer a defect to a faulty circuit, simulation of the faulty circuit would tell us if a particular testing scheme would interpret it as such. Second, they are useful in predicting the probability of occurrence of faults, which in turn is useful in predicting yield and designing test vectors. Validity of high level models like Single Line Stuck At 0/1 can also thus be evaluated. This paper raises a number of unsolved issues in circuit level modeling of defects.
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[Proceedings] 1991 International Workshop on Defect and Fault Tolerance on VLSI Systems
