Adaptive Design for Performance-Optimized Robustness**This work was supported in part by the IBM Faculty Partnership Award Program, and in part by the Gigascale Systems Research Center at UC Berkeley under contract 2003-DT-660 from Microelectronics Advanced Research Corporation (MARCO). Conference Paper uri icon


  • We present adaptive design techniques that compensate for manufacturing induced process variations in Deep Sub-micron (DSM) Integrated Circuits. Process variations have a significant impact on parametric behavior of modern chips, and adaptive design techniques that make a chip self-configuring to work optimally across process corners are fast evolving as a potential solution to this problem. Such schemes have two main components, a mechanism for sensing process perturbations, and one or more process compensation schemes that are driven by this mechanism. The adaptive design schemes presented in this paper are simple, low overhead techniques for noise tolerance in DSM CMOS circuits, to enhance their manufacturing yield. The process perturbation sensing scheme is based on on-chip delay measurement with a performance based bound on adaptation, which enables performance optimized robustness to noise in the face of process variations. 2006 IEEE.

name of conference

  • 2006 21st IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

published proceedings

  • 2010 IEEE 25th International Symposium on Defect and Fault Tolerance in VLSI Systems

author list (cited authors)

  • Datta, R., Abraham, J. A., Diril, A. U., Chatterjee, A., & Nowka, K.

citation count

  • 5

complete list of authors

  • Datta, Ramyanshu||Abraham, Jacob A||Diril, Abdulkadir Utku||Chatterjee, Abhijit||Nowka, Kevin

publication date

  • October 2006