Fault probability prediction for array based designs
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abstract
Application-specific integrated circuits (ASICs) are frequently implemented using a fixed base array personalized with metal interconnect, permitting rapid turnaround. For any particular design, the array cannot be fully-utilized, due to limitations on gate, routing, and pin resources, or the limited number of array sizes. In some array designs, such as sea-of-gates, 100% array utilization is not possible since much of the array area will be used for routing. This partial array utilization makes yield prediction difficult. Traditional area-based yield models underestimate array yield since they assume that all defects that occur in unused portions of the array will be fatal, when most will not. Reducing the critical area by the utilization factor will overestimate yield, since some defects cause fatal circuit faults even when they occur in unused sections of the array. These yield errors can result in uncompetitive designs and lost profits. Accurate prediction of array-based ASIC yield requires an understanding of how defects interact with the base array and its personalization to cause fatal circuit faults. In this paper we describe a methodology to accurately predict the probability of fatal faults and yield in array-based ASICs using the DEFAM defect to fault mapper. We demonstrate the use of this methodology on several versions of a sea-of-gates array design, showing how traditional methods both overestimate and underestimate the actual yield.
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Proceedings. 1996 IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems
