Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric Conference Paper uri icon

abstract

  • This paper proposes a realistic low cost fault coverage metric targeting both global and local delay faults. It suggests the test strategy of generating a different number of the longest paths for each line in the circuit while maintaining high fault coverage. This metric has been integrated into the CodGen ATPG tool. Experimental results show significant reductions in test generation time and vector count on ISCAS89 and industry designs. © 2009 IEEE.

author list (cited authors)

  • Wang, Z., & Walker, D.

citation count

  • 4

publication date

  • May 2009

publisher