Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric Conference Paper

abstract

• This paper proposes a realistic low cost fault coverage metric targeting both global and local delay faults. It suggests the test strategy of generating a different number of the longest paths for each line in the circuit while maintaining high fault coverage. This metric has been integrated into the CodGen ATPG tool. Experimental results show significant reductions in test generation time and vector count on ISCAS89 and industry designs. 2009 IEEE.

name of conference

• 2009 27th IEEE VLSI Test Symposium

authors

• Walker, Duncan

published proceedings

• 2009 27TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS

author list (cited authors)

• Wang, Z., & Walker, D.

citation count

• 5

complete list of authors

• Wang, Zheng||Walker, DMH

publication date

• May 2009

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• n1093-0167ISSN  Journal

keywords

• 40 Engineering
• 4008 Electrical Engineering

Digital Object Identifier (DOI)

• 10.1109/VTS.2009.55

International Standard Book Number (ISBN) 13

• 9780769535982

start page

• 59

end page

• 64

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fvts.2009.55