Improvement of SRAM-based failure analysis using calibrated Iddq testing Conference Paper

abstract

• This work presents a methodology to identify integrated circuit yield detractors using SRAM functional test results in combination with a defect-bitmap dictionary. We investigate the accuracy of the defect classification under different forms of voltage testing and current testing. In particular we investigate the benefit of using multiple Iddq current levels calibrated to remove normal parametric variations. We also investigate the effects of unmodeled defects and the ability to identify cases of certain and uncertain diagnosis. We have experimentally validated our approach using a production microprocessor cache.

name of conference

• Proceedings of 14th VLSI Test Symposium

authors

• Walker, Duncan

published proceedings

• 14TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS

author list (cited authors)

• Balachandran, H., & Walker, D.

citation count

• 15

complete list of authors

• Balachandran, H||Walker, DMH

publication date

• January 1996

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• n1093-0167ISSN  Journal

keywords

• 40 Engineering
• 4009 Electronics, Sensors And Digital Hardware

Digital Object Identifier (DOI)

• 10.1109/VTEST.1996.510847

International Standard Book Number (ISBN) 10

• 0-8186-7304-4

start page

• 130

end page

• 136

URL

• http://dx.doi.org/10.1109/vtest.1996.510847