Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits

2014 by Taylor & Francis Group, LLC. Delay testing detects small manufacturing defects that do not cause functional failure but affect the speed of integrated circuits. The path delay fault model [Smith 1985] is the most conservative of the classical delay fault models because a circuit is faulty if any path delay exceeds the specification time. The problem with this model is that the paths in real circuits cannot be enumerated. To overcome this problem, some test methods only cover a subset of the paths (e.g., the global longest paths) [Lin 1987; Bell 1996] or the longest path through each gate [Li 1989; Majhi 2000; Murakami 2000; Shao 2002; Sharma 2002]. A delay fault caused by a local defect, such as a resistive open or short, can only be detected by testing a path through it, and testing the longest path through it can detect the smallest local delay defect. Process variation and noise can result in the longest path through a gate varying from chip to chip or across operating conditions. Therefore, testing only one path through each gate cannot guarantee the detection of the smallest local.

Testing for Small-Delay Defects in Nanoscale CMOS Integrated Circuits Chapter