Statistical Static Timing Analysis Considering the Impact of Power Supply Noise in VLSI Circuits Conference Paper

abstract

• As semiconductor technology is scaled and voltage level is reduced, the impact of power supply variation has become very significant in predicting the realistic worstcase delays in integrated circuits. The analysis of power supply noise is inevitable since there is a high correlation between delay and supply voltage. Supply noise analysis has often used a vector-based STA approach. However, vector-based approaches are very expensive, particularly during the design phase. In this work, two novel vectorless approaches are described such that circuit delay increases due to power supply noise can be efficiently estimated. Experimental results on ISCAS89 circuits show not only the accuracy of our approaches, but also the indispensability of considering care-bits, which sensitize the longest paths during the power supply noise analysis. 2006 IEEE.

name of conference

• Seventh International Workshop on Microprocessor Test and Verification (MTV'06)

authors

• Walker, Duncan

published proceedings

• 2013 14th International Workshop on Microprocessor Test and Verification

author list (cited authors)

• Kim, H. S., & Walker, D.

citation count

• 10

complete list of authors

• Kim, Hyun Sung||Walker, DMH

publication date

• December 2006

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Proceedings - International Workshop on Microprocessor Test and Verification  Journal

keywords

• Power Supply Noise
• Statistical Static Timing Analysis

Digital Object Identifier (DOI)

• 10.1109/mtv.2006.20

International Standard Book Number (ISBN) 10

• 0769526896

International Standard Book Number (ISBN) 13

• 9780769526898

URI

• https://hdl.handle.net/1969.1/ETD-TAMU-1902

start page

• 76

end page

• 82

URL

• http://dx.doi.org/10.1109/mtv.2006.20