Detection of bridging faults in logic resources of configurable FPGAs using I-DDQ Conference Paper

abstract

• This paper presents an IDDQ-based test strategy for detecting bridging faults in the logic resources of reprogrammable Field Programmable Gate Arrays (FPGAs). The approach utilizes the programmability of the Configurable Logic Blocks (CLBs) to achieve 100% coverage of IDDQ-testable bridging faults. Since reconfiguration programming time can dominate total test time, even with slow IDDQvectors, we use a bottom-up test generation approach to minimize the number of programming phases first, and then to minimize the number of test vectors. 100% coverage for IDDQ-testable bridging faults is achieved in 5 programming phases and 16 IDDQvectors in the Xilinx XC4000 FPGA family. The RAM modes are tested in a further phase, using 48 test vectors and 38 IDDQmeasurements.

name of conference

• Proceedings International Test Conference 1998 (IEEE Cat. No.98CH36270)

authors

• Walker, Duncan

published proceedings

• INTERNATIONAL TEST CONFERENCE 1998, PROCEEDINGS

author list (cited authors)

• Zhao, L., Walker, D., & Lombardi, F.

citation count

• 15

complete list of authors

• Zhao, L||Walker, DMH||Lombardi, F

publication date

• January 1998

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• International Test Conference  Journal

keywords

• Bridging Fault
• Configurable Logic Blocks
• Fpga
• I-ddq Test
• Programming Phase
• Testing

Digital Object Identifier (DOI)

• 10.1109/TEST.1998.743302

International Standard Book Number (ISBN) 10

• 0-7803-5093-6

start page

• 1037

end page

• 1046

URL

• http://dx.doi.org/10.1109/test.1998.743302