Improved Wafer-level Spatial Analysis for IDDQ Limit Setting Conference Paper uri icon


  • This paper proposes a new methodology for estimating the upper bound on the IDDQ of defect free chips by using wafer level spatial information. This can be used for IDDQ pass/fail limit setting. This methodology is validated using SEMATECH data. Such a methodology accounts for the change in IDDQ due to process variations across wafers and reduces false rejects resulting in yield loss. Typical scenarios in using this approach are discussed. The results are compared with traditional methods.

author list (cited authors)

  • Sabade, S., & Walker, D.

citation count

  • 31

publication date

  • January 2001