Improved wafer-level spatial analysis for I-DDQ limit setting Conference Paper

abstract

• This paper proposes a new methodology for estimating the upper bound on the IDDQ of defect free chips by using wafer level spatial information. This can be used for IDDQ pass/fail limit setting. This methodology is validated using SEMATECH data. Such a methodology accounts for the change in IDDQ due to process variations across wafers and reduces false rejects resulting in yield loss. Typical scenarios in using this approach are discussed. The results are compared with traditional methods.

name of conference

• Proceedings International Test Conference 2001 (Cat. No.01CH37260)

authors

• Walker, Duncan

published proceedings

• INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS

author list (cited authors)

• Sabade, S., & Walker, D.

citation count

• 31

complete list of authors

• Sabade, S||Walker, DMH

publication date

• January 2001

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• International Test Conference  Journal

keywords

• 40 Engineering
• 4014 Manufacturing Engineering

Digital Object Identifier (DOI)

• 10.1109/TEST.2001.966621

International Standard Book Number (ISBN) 10

• 0-7803-7169-0

start page

• 82

end page

• 91

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ftest.2001.966621