Pseudo Functional Path Delay Test through Embedded Memories Academic Article uri icon


  • 2014, Springer Science+Business Media New York. Memory arrays cannot be as easily tested as other storage elements. They can be considered as non-scan cells. Memory built-in self-test (MBIST), functional test, and macro test are used to test memory arrays. However, these methods do not focus on the interaction between memory and surrounding logic, so may not cover timing critical paths. In this paper, we propose path delay test through memory arrays using pseudo functional test with K Longest Paths Per Gate (PKLPG). Long paths captured into a non-scan cell (including a memory cell) are propagated to a scan cell or primary output, and non-scan cells are initialized so that they can launch transitions onto long paths. This allows scan tests to cover critical paths into and out of memory arrays.

published proceedings

  • Journal of Electronic Testing

author list (cited authors)

  • Gao, Y., Zhang, T., Pokharel, P., Chakraborty, S., & Walker, D.

citation count

  • 0

complete list of authors

  • Gao, Yukun||Zhang, Tengteng||Pokharel, Punj||Chakraborty, Swati||Walker, DMH

publication date

  • February 2015