ARCHITECTURES FOR CATASTROPHIC AND DELAY FAULT-TOLERANCE
Conference Paper
Overview
Identity
Additional Document Info
View All
Overview
abstract
Wafer-scale architectures have defect tolerance as one of their primary goals. To date only architectures tolerant of spot defects (e.g. oxide pinholes, extra and missing material) that cause catastrophic circuit faults, (e.g. shorts, opens) and functional yield loss have been considered. Anecdotal data and simulation experiments indicate that as geometries shrink, delay faults caused by spot defects will become increasingly important, and must be tolerated in order for wafer-scale architectures to have acceptable parametric yield. This paper presents approaches to designing architectures that possess both catastrophic and delay fault tolerance.
