IC performance prediction for test cost reduction Academic Article

abstract

• 1999 IEEE. This paper describes a methodology for building models predicting manufactured integrated circuit performances as a function of inline and wafer electrical test measurements. We show how these predictions can be used to predict the performance of an industrial microprocessor, and reduce the average number of speed bins that must be tested by 45%.

authors

• Walker, Duncan

published proceedings

• ASIC, 2003 Proceedings 5th International Conference on

author list (cited authors)

• Lee, J., Walker, D., Milor, L., Peng, Y., & Hill, G.

citation count

• 12

complete list of authors

• Lee, Jungran||Walker, DMH||Milor, L||Peng, Yeng||Hill, G

publication date

• January 1999

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International Symposium on Semiconductor Manufacturing Conference Proceedings  Journal

Digital Object Identifier (DOI)

• 10.1109/issm.1999.808750

start page

• 111

end page

• 114

URL

• http://dx.doi.org/10.1109/issm.1999.808750