This chapter describes the common delay test approaches, with a focus on structural delay testing using two-pattern tests, where transitions are launched into the circuit and then the results are captured within the rated clock cycle time. The use of design-for-test features such as scan chains provides the controllability and observability to make structural testing practical. This is combined with a slow scan in of the initialization vector, then application of the test vector via launch-on-shift or launch-on-capture, and then capture of the results. With knowledge of the expected path delays, faster-than-at-speed testing can be used to increase detection of small delay defects. Traditional delay fault models, the transition fault, gate-delay fault, and path-delay fault, as well as newer models are also presented, including inline delay fault, propagation delay fault, segment delay fault, and defect-based delay fault models. The quality of tests in terms of test sensitization is discussed. Sensitization is particularly important when testing for small delay defects. An increasing challenge in delay testing is to achieve high coverage of small delay defects and good correlation to functional test results. A major part of it is to account for supply noise during delay testing. A further challenge is achieving this coverage in the presence of process variation, which increases the number of potentially longest paths in the circuit. 2008 Elsevier Inc. All rights reserved.
