Estimation of fault-free leakage current using wafer-level spatial information Academic Article

abstract

• Leakage current or the IDDQ test has been shown to be an effective test screen in combination with traditional test methods. However, leakage current is rising rapidly as semiconductor technology advances. This makes it difficult to distinguish between faulty and fault-free chips using traditional threshold setting methods. This paper presents a method to estimate leakage current using neighboring chip information on a wafer. Outlier chips are rejected, and a least-squares-fit plane through neighboring chips is used to estimate defect-free IDDQ. Chips that significantly deviate from the estimate are rejected. The proposed method is evaluated using industrial test data. 2006 IEEE.

authors

• Walker, Duncan

published proceedings

• IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS

author list (cited authors)

• Sabade, S. S., & Walker, D.

citation count

• 5

complete list of authors

• Sabade, SS||Walker, DMH

publication date

• January 2006

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

keywords

• I-ddq Testing
• Pass/fail Limit Setting
• Spatial Correlation

Digital Object Identifier (DOI)

• 10.1109/TVLSI.2005.863183

start page

• 91

end page

• 94

volume

• 14

issue

• 1

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ftvlsi.2005.863183