SOFT-PROGRAMMABLE BYPASS SWITCH DESIGN FOR DEFECT-TOLERANT ARRAYS

The issues in bypass and wiring design include routing flexibility, yield, area, and signal delay. Ideally sufficient wiring resources are available to always map the desired array onto the set of good module sites. Since defects are clustered, it may be the case that several neighboring sites are bad, and the wiring must have the ability to connect two modules separated by several bad sites. Bypass circuit yield should be as high as possible. The higher the yield, the fewer wiring resources necessary to route a wafer. In some designs, bypass circuit yield must be 100%. The bypass circuitry should take a minimum amount of area. A large area will result in lower bypass circuit yield and thus wafer yield, and will also reduce the number of modules per wafer. The bypass circuitry must have a small signal delay. In wafer-scale arrays, the module size is typically small and can potentially operate at a high clock frequency. In most designs, signals must propagate from one module to another in less than one clock cycle. A number of switch designs are proposed and analyzed to see how well they meet the ideal design goals. Some directions on future work are given.

SOFT-PROGRAMMABLE BYPASS SWITCH DESIGN FOR DEFECT-TOLERANT ARRAYS Conference Paper