Defect localization using physical design and electrical test information Conference Paper

abstract

• In this work we describe an approach of using physical design and test failure knowledge to localize defects in random logic. We term this approach computer-aided fault to defect mapping (CAFDM). An integrated tool has been developed on top of an existing commercial ATPG tool. CAFDM was able to correctly identify the defect location and layer in all 9 of the chips that had bridging faults injected via FIB. Preliminary failure analysis results on production defects are promising. 2000 IEEE/SEMl Advanced Semiconductor Manufacturing Conference.

name of conference

• 2000 IEEE/SEMI Advanced Semiconductor Manufacturing Conference and Workshop. ASMC 2000 (Cat. No.00CH37072)

authors

• Walker, Duncan

published proceedings

• 2000 IEEE/SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE AND WORKSHOP

author list (cited authors)

• Stanojevic, Z., Balachandran, H., Walker, D., Lakhani, F., & Jandhyala, S.

citation count

• 4

complete list of authors

• Stanojevic, Z||Balachandran, H||Walker, DMH||Lakhani, F||Jandhyala, S

publication date

• January 2000

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• ASMC (Advanced Semiconductor Manufacturing Conference) Proceedings  Journal

keywords

• Defect Diagnosis
• Defect Isolation
• Defect Localization
• Failure Analysis
• Fault Diagnosis
• Fault Isolation
• Fault Localization
• Testing

Digital Object Identifier (DOI)

• 10.1109/ASMC.2000.902568

International Standard Book Number (ISBN) 10

• 0-7803-5921-6

start page

• 108

end page

• 115

volume

• 2000-January

URL

• http://dx.doi.org/10.1109/asmc.2000.902568