FFATA: SHF: Small: High Quality Test and Post-Silicon Validation of System-On-Chip Integrated Circuits
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Testing microprocessors and other chips to verify their clock rate is known as delay testing. If the test is wrong, and a 3 GHz chip is really a 2.99 GHz chip, the customer system may randomly crash. But if the test is wrong and a 2.8 GHz chip will really run at 3 GHz, the manufacturer loses money by selling the 3 GHz chip as a lower-priced 2.8 GHz chip. Today it is expensive to accurately determine the clock rate of high-speed chips. This project is developing new test techniques to lower the cost of accurate manufacturing tests, so that chip prices can be reduced. Accurate delay testing becomes even more challenging when chips are stacked together in products such as cell phones and tablets, since noise from one chip can influence the speed of its neighbors. The broader impact of this project is in educating students to do advanced development and research in the semiconductor and electronics industries, both by directly working on the project, and through courses that use the project results. The results of this research will be distributed to academia and industry. A longer-term broader impact is acceleration of cost reductions in stacked chips in advanced consumer products, providing more functionality at an affordable price with desirable weight, size, and battery life.