Accurate yield estimation of circuits with redundancy Conference Paper

abstract

• Yield concerns owing to increasing die sizes have prompted designers to include redundant elements in the design. In this paper we present a technique for accurately estimating the yield of designs that employ redundancy. We show that conventional techniques that do not take into account the actual chip layout and defect statistics could result in substantial error in the yield estimate. We show that the optimum amount and nature of redundancy depends heavily on the nature of the circuit, the chip layout and defect statistics.

name of conference

• Proceedings of International Workshop on Defect and Fault Tolerance in VLSI

authors

• Walker, Duncan

published proceedings

• Proceedings IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems

author list (cited authors)

• Gaitonde, D. D., Walker, D., & Maly, W.

citation count

• 2

complete list of authors

• Gaitonde, DD||Walker, DMH||Maly, W

publication date

• January 1995

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems  Journal

Digital Object Identifier (DOI)

• 10.1109/dftvs.1995.476948

start page

• 155

end page

• 163

URL

• http://dx.doi.org/10.1109/dftvs.1995.476948