Use of multiple I-DDQ test metrics for Outlier identification Conference Paper

abstract

• 2003 IEEE. With increasing circuit complexity and reliability requirements, screening outlier chips is an increasingly important test challenge. This is especially true for IDDQ test due to increased spread in the distribution. In this paper, the concept of current ratio is extended to exploit wafer-level spatial correlation. Two metrics - current ratio and neighbor current ratio - are combined to screen outliers at the wafer level. We demonstrate that a single metric alone cannot screen all outliers, however, their combination can be used for effectively screening outlier chips. Analyses based on industrial test data are presented.

name of conference

• Proceedings. 21st VLSI Test Symposium, 2003.

authors

• Walker, Duncan

published proceedings

• 21ST IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS

author list (cited authors)

• Sabade, S. S., & Walker, D.

citation count

• 9

complete list of authors

• Sabade, SS||Walker, DMH

publication date

• January 2003

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• n1093-0167ISSN  Journal

keywords

• Current Ratio
• I-ddq Testing
• Neighbor Current Ratio
• Outlier Identification
• Spatial Correlation

Digital Object Identifier (DOI)

• 10.1109/VTEST.2003.1197630

International Standard Book Number (ISBN) 10

• 0-7695-1924-5

start page

• 31

end page

• 38

volume

• 2003-January

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fvtest.2003.1197630