publication venue for
- Simulation-based design error diagnosis and correction in combinational digital circuits. 70-78. 1999
- Special Session: Countering IP Security threats in Supply chain 2019
- Special Session: Recent Developments in Hardware Security 2018
- Improved Power Supply Noise Control for Pseudo Functional Test 2014
- Power Supply Noise Control in Pseudo Functional Test 2013
- Levelized Low Cost Delay Test Compaction Considering IR-Drop Induced Power Supply Noise 2011
- Compact Delay Test Generation with a Realistic Low Cost Fault Coverage Metric 2009
- Dynamic compaction for high quality delay test 2008
- A CMOS RF RMS detector for built-in testing of wireless transceivers 2005
- Static compaction of delay tests considering power supply noise 2005
- A statistical fault coverage metric for realistic path delay faults 2004
- An on-chip transfer function characterization system for analog built-in testing 2004
- Comparison of NCR effectiveness with a reduced I-DDQ vector set 2004
- A circuit level fault model for resistive opens and bridges 2003
- Use of multiple I-DDQ test metrics for Outlier identification 2003
- Evaluation of effectiveness of median of absolute deviations outlier rejection-based I-DDQ testing for burn-in reduction 2002
- High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor 1998
- Improvement of SRAM-based failure analysis using calibrated Iddq testing 1996
- Optimal voltage testing for physically-based faults 1996