Model-based I-DDQ pass/fail limit setting Conference Paper

abstract

• 1998 IEEE. This paper describes several methods for setting LDDQ pass/fail limits using cell-based process, circuit and logic simulation. We demonstrate trade-offs in accuracy and model building effort on the ISCAS85 circuits.

name of conference

• Proceedings 1998 IEEE International Workshop on IDDQ Testing (Cat. No.98EX232)

authors

• Walker, Duncan

published proceedings

• 1998 IEEE INTERNATIONAL WORKSHOP ON IDDQ TESTING, PROCEEDINGS

author list (cited authors)

• Unni, T. A., & Walker, D.

citation count

• 13

complete list of authors

• Unni, TA||Walker, DMH

publication date

• January 1998

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

keywords

• 40 Engineering
• 4010 Engineering Practice And Education

Digital Object Identifier (DOI)

• 10.1109/IDDQ.1998.730731

International Standard Book Number (ISBN) 10

• 0-8186-9191-3

International Standard Book Number (ISBN) 13

• 9780818691911

start page

• 43

end page

• 47

volume

• 1998-November

URL

• http://dx.doi.org/10.1109/iddq.1998.730731