Technology Scaling Issues of an IDDQ Built-In Current Sensor
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abstract
Analysis and comparison of 1.5 m and 350 nm CMOS test chip results of a built-in current sensor design reveal several critical design issues. This paper includes a discussion of these issues. The success of the sensor design hinges on how these issues are addressed in order to achieve successful operation during technology scaling.
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Proceedings. 2005 IEEE International Workshop on Current and Defect Based Testing, 2005. DBT 2005.