Fault coverage analysis for physically-based CMOS bridging faults at different power supply voltages Conference Paper uri icon


  • Bridging faults in CMOS circuits sometimes degrade the output voltage and time performance without altering the logic function. The traditional voltage testing models based on the normal power supply voltage do not accurately model this behavior. In this paper we develop a model of bridging faults that accounts for both the bridging resistance distribution and gate sensitization and propagation choices. This model shows that fault coverage increases at lower power supply voltages. It suggests that decreasing the power supply voltage is a promising technique to maximize the real fault coverage of voltage tests, thereby minimizing the number of relatively slow Iddq tests required to achieve high quality.

name of conference

  • Proceedings International Test Conference 1996. Test and Design Validity

published proceedings

  • IEEE International Test Conference (TC)

author list (cited authors)

  • Liao, Y. Y., & Walker, D.

citation count

  • 33

complete list of authors

  • Liao, YY||Walker, DMH

publication date

  • December 1996