Dynamic compaction for high quality delay test Conference Paper

abstract

• Dynamic compaction is an effective way to reduce the number of test patterns while maintaining high fault coverage. This paper proposes a new dynamic compaction algorithm for generating compacted test sets for K longest paths per gate (KLPG) in combinational circuits or scan-based sequential circuits. This algorithm uses a greedy approach to compact paths with non-conflicting assignments together during test generation. Experimental results for ISCAS89 benchmark circuits and two industry circuits show that the pattern count of KLPG can be significantly reduced (up to 3x compared to static compaction) using the proposed method. The pattern count after dynamic compaction is comparable to the number of transition fault tests, while achieving higher test quality. 2008 IEEE.

name of conference

• 26th IEEE VLSI Test Symposium (vts 2008)

authors

• Walker, Duncan

published proceedings

• 26TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS

author list (cited authors)

• Wang, Z., & Walker, D.

citation count

• 25

complete list of authors

• Wang, Zheng||Walker, DMH

publication date

• April 2008

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• n1093-0167ISSN  Journal

keywords

• Delay Test
• Dynamic Compaction
• Path Delay Fault
• Test Generation

Digital Object Identifier (DOI)

• 10.1109/VTS.2008.54

International Standard Book Number (ISBN) 13

• 978-0-7695-3123-6

start page

• 243

end page

• 248

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Fvts.2008.54