Comparison of Delay Tests on Silicon Conference Paper

abstract

• Testing longer paths in an integrated circuit with a proper path selection strategy has the potential to increase the quality of a delay test. However, the benefit on silicon is not completely clear because a theoretical test quality increase is normally simulated using an assumed distribution of defect sizes. In this work, silicon data is collected and maximum operating frequency (Fmax) compared using test patterns generated by a variety of delay test methodologies. The silicon data is consistent with theoretical predictions and the benefits of testing delay faults through the longest path are quantified. 2006 IEEE.

name of conference

• 2006 IEEE International Test Conference

authors

• Walker, Duncan

published proceedings

• International Test Conference 1999 Proceedings (IEEE Cat No99CH37034)

author list (cited authors)

• Qiu, W., Walker, D., Simpson, N., Reddy, D., & Moore, A.

citation count

• 5

complete list of authors

• Qiu, Wangqi||Walker, DMH||Simpson, Neil||Reddy, Divya||Moore, Anthony

publication date

• October 2006

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• International Test Conference  Journal

Digital Object Identifier (DOI)

• 10.1109/test.2006.297624

International Standard Book Number (ISBN) 10

• 1424402921

International Standard Book Number (ISBN) 13

• 9781424402922

start page

• 1

end page

• 10

URL

• http%3A%2F%2Fdx.doi.org%2F10.1109%2Ftest.2006.297624