Optimizing VMIN of ROM Arrays Without Loss of Noise Margin Conference Paper uri icon

abstract

  • Copyright 2015 ACM. The minimum voltage of operation (Vmin) for memory arrays often limits the lowest system operating voltage. This paper introduces a novel read assist topology for a domino-based evaluation architecture in a read only memory (ROM). The implementation incorporates an assist pull-down (PD) device, which activates during the evaluation phase in order to increase the effective pull-down strength of the bit cells. This implementation maintains Vmin without increasing the size of pull down devices inside the bit cells. The assist topology improves read delay by 11-30% and increases noise margin. Area overhead can be limited to 27% in a typical ROM.

altmetric score

  • 3

author list (cited authors)

  • Chakraborty, A., & Walker, D.

citation count

  • 0

publication date

  • May 2015

publisher

  • ACM  Publisher