Logic and fault simulation
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This chapter deals with logic simulation. The popular compiled-code and event-driven logic simulation techniques are addressed in the chapter. It also provides description of hazards, the undesirable transient pulses (glitches) that can occur in circuits, what causes them, and how they can be detected during logic simulation. The chapter then discusses fault simulation. Fault simulation is rooted in logic simulation; many techniques have been developed to quickly simulate all possible faulty behaviors. Moreover, a discussion of the serial, parallel, deductive, concurrent, and differential fault simulation techniques is presented, followed by qualitative comparisons between their advantages and drawbacks. The chapter concludes with alternative techniques to fault simulation. These techniques trade accuracy for reduced execution time, which is crucial for managing the complexity of large designs. © 2006 Elsevier Inc. All rights reserved.
author list (cited authors)
Huang, J. L., Li, J., & Walker, D. M.
VLSI Test Principles and Architectures