Test generation for global delay faults Conference Paper

abstract

• This paper describes test generation for delay faults caused by global process disturbances. The correlations between path delays is used to reduce the number of paths that must be tested. We build macro models of path delays as a function of process parameters to reduce test generation time. The test generation problem is formulated as a nonlinear optimization using a set of candidate paths supplied by a path generator. Results are given for the ISCAS85 benchmarks.

name of conference

• Proceedings International Test Conference 1996. Test and Design Validity

authors

• Walker, Duncan

published proceedings

• INTERNATIONAL TEST CONFERENCE 1996, PROCEEDINGS

author list (cited authors)

• Luong, G. M., & Walker, D.

citation count

• 25

complete list of authors

• Luong, GM||Walker, DMH

publication date

• January 1996

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• International Test Conference  Journal

keywords

• 40 Engineering
• 4010 Engineering Practice And Education

Digital Object Identifier (DOI)

• 10.1109/TEST.1996.557048

International Standard Book Number (ISBN) 10

• 0-7803-3541-4

start page

• 433

end page

• 442

URL

• http://dx.doi.org/10.1109/test.1996.557048