Application of defect simulation as a tool for more efficient failure analysis
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In modern VLSI processes, increasing process complexity has resulted in an exponential rise in the costs of thorough failure analysis. In this paper, we present a defect simulation‐based failure analysis methodology, which can be used to significantly reduce both costs and turn‐around time for failure analyses. The methodology is based on the ability to generate a defect dictionary, which can relate defect characteristics to some easily measurable symptoms of defect occurrence. Copyright © 1994 John Wiley & Sons, Ltd.
author list (cited authors)
Griep, S., Khare, B., Lemme, R., Papenberg, U., Schmitt‐Landsiedel, D., Maly, W., ... Zettler, T.