HR job title
- Professor of the Practice
- Contact Info
Nowka, Kevin Professor of the Practice
Positions
- Professor of the Practice, Electrical and Computer Engineering, College of Engineering
- Overview
- Publications
- Teaching
- Works By Students
- Background
- Contact
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Overview
Publications
selected publications
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academic article
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Gebara, F. H., Hofstee, H. P., & Nowka, K. J.
(2015).
Second-Generation Big Data Systems. Computer.
48(1), 36-41.
-
Kuang, J. B., Schaub, J. D., Gebara, F. H., Wendel, D., Frhnel, T., Saroop, S., Nassif, S., & Nowka, K.
(2011).
The Design and Characterization of a Half-Volt 32 nm Dual-Read 6T SRAM. 58(9), 2010-2016.
-
Datta, R., Sebastine, A., Raghunathan, A., Carpenter, G., Nowka, K., & Abraham, J. A.
(2010).
On-Chip Delay Measurement Based Response Analysis for Timing Characterization. Journal of Electronic Testing.
26(6), 599-619.
-
Kim, K., Kuang, J. B., Gebara, F. H., Ngo, H. C., Chuang, C., & Nowka, K. J.
(2009).
TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability. IEEE Transactions on Electron Devices.
56(12), 3033-3040.
-
Kuang, J. B., Kim, K., Chuang, C., Ngo, H. C., Gebara, F. H., & Nowka, K. J.
(2008).
Circuit Techniques Utilizing Independent Gate Control in Double-Gate Technologies. IEEE Transactions on Very Large Scale Integration Systems.
16(12), 1657-1665.
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Singh, H., Agarwal, K., Sylvester, D., & Nowka, K. J.
(2007).
Enhanced leakage reduction techniques using intermediate strength power gating. IEEE Transactions on Very Large Scale Integration Systems.
15(11), 1215-1224.
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Kim, K., Chuang, C., Kuang, J. B., Ngo, H. C., & Nowka, K. J.
(2007).
Low-power high-performance asymmetrical double-gate circuits using back-gate-controlled wide-tunable-range diode voltage. IEEE Transactions on Electron Devices.
54(9), 2263-2268.
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Sapatnekar, S., & Nowka, K.
(2005).
Guest Editors' Introduction: New Dimensions in 3D Integration. IEEE Design and Test.
22(6), 496-497.
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Nowka, K. J., Carpenter, G. D., & Brock, B. C.
(2003).
The design and application of the PowerPC 405LP energy-efficient system-on-a-chip. IBM Journal of Research and Development.
47(5-6), 631-639.
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Nowka, K. J., Carpenter, G. D., MacDonald, E. W., Ngo, H. C., Brock, B. C., Ishii, K. I., Nguyen, T. Y., & Burns, J. L.
(2002).
A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. IEEE Journal of Solid-State Circuits.
37(11), 1441-1447.
-
Kwon, O., Nowka, K., & Swartzlander, E. E.
(2002).
A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells. Journal of Signal Processing Systems.
31(2), 77-89.
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Nowka, K., Carpenter, G., Donald, E. M., Ngo, H., Brock, .., Ishii, K., Nguyen, T., & Burns, J.
(2002).
A 0.9V to 1.95V Dynamic Voltage-Scalable and Frequency-Scalable 32b PowerPC Processor. Digest of technical papers / IEEE International Solid-State Circuits Conference. IEEE International Solid-State Circuits Conference.
1, 1-2.
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Allen, D. H., Dhong, S. H., Hofstee, H. P., Leenstra, J., Nowka, K. J., Stasiak, D. L., & Wendel, D. F.
(2000).
Custom circuit design as a driver of microprocessor performance. IBM Journal of Research and Development.
44(6), 799-822.
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Silberman, J., Aoki, N., Boerstler, D., Burns, J. L., Dhong, S., Essbaum, A., ... Zoric, B.
(1998).
A 1.0-GHz single-issue 64-bit powerPC integer processor. IEEE Journal of Solid-State Circuits.
33(11), 1600-1608.
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Hofstee, H. P., Dhong, S. H., Meltzer, D., Nowka, K. J., Silberman, J. A., Burns, J. L., Posluszny, S. D., & Takahashi, O.
(1998).
Designing for a gigahertz. IEEE Micro.
18(3), 66-74.
-
Gebara, F. H., Hofstee, H. P., & Nowka, K. J.
(2015).
Second-Generation Big Data Systems. Computer.
48(1), 36-41.
-
chapter
-
Nowka, K. J.
(2017).
Issues in High-Frequency Processor Design. Digital Design and Fabrication.
10-1-10-16.
Taylor & Francis.
-
Swartzlander, E. E., & Lemonds, C. E.
(2015).
Computer Arithmetic. Computer Arithmetic.
(pp. 1-474).
WORLD SCIENTIFIC.
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Nowka, K. J.
(2008).
Issues in High-Frequency Processor Design. DIGITAL DESIGN AND FABRICATION.
10-1-10-16.
-
Nowka, K. J.
(2001).
Issues in high-frequency processor design. The Computer Engineering Handbook.
13-1-13-15.
-
Nowka, K. J.
(2017).
Issues in High-Frequency Processor Design. Digital Design and Fabrication.
10-1-10-16.
Taylor & Francis.
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conference paper
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Zhal, L., Bhandri, M., Um, D., Nowka, K., Landivar, J., & Ladivar, J. L.
(2023).
Plant Height Estimation using Satellite/UAV Data Fusion and Machine Learning. 314-1-314-2.
-
Gadepally, K. C., Dhal, S. B., Kalafatis, S., & Nowka, K. J.
(2023).
Realistic Predictors for Regression and Semantic Segmentation. 153-155.
-
Dhal, S. B., Mahanta, S., Gadepally, K. C., He, S., Hughes, M., Moore, J., Nowka, K. J., & Kalafatis, S.
(2023).
CNN-based real-time prediction of growth stage in soybeans cultivated in hydroponic set-ups. 193-197.
-
Gadepally, K. C., Dhal, S. B., Bhandari, M., Landivar, J., Kalafatis, S., & Nowka, K.
(2023).
A Deep Transfer Learning based approach for forecasting spatio-temporal features to maximize yield in cotton crops. 1-4.
-
Kalafatis, S., Nowka, K., & Lusher, J.
(2022).
Tools and Methods for enabling senior design classes during the COVID19 pandemic and their application to future challenges. 1-11.
-
Nowka, K. J.
(2012).
Transforming Memory Systems: Optimizing for Client Value on Emerging Workloads. 1-2.
-
Nowka, K. J.
(2012).
Transforming Memory Systems: Optimizing for Client Value on Emerging Workloads. International Symposium on VLSI Technology, Systems, and Applications, Proceedings.
1-2.
-
Kuang, J. B., Schaub, J. D., Gebara, F. H., Wendel, D., Saroop, S., Nguyen, T., ... Nowka, K. J.
(2010).
A 32nm 0.5V-Supply Dual-Read 6T SRAM. Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference.
1-4.
-
Nowka, K.
(2010).
Technology variability and uncertainty implications for power- efficient VLSI systems. 239-240.
-
Agarwal, K., Hayes, J., Barth, J., Jacunski, M., Nowka, K., Kirihata, T., & Iyer, S.
(2010).
In-situ Measurement of Variability in 45-nm SOI Embedded DRAM Arrays. 189-190.
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Nassif, S. R., & Nowka, K. J.
(2010).
Physical design challenges beyond the 22nm node. 13-14.
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Kanj, R., Joshi, R., Kuang, J. B., Kim, J., Meterelliyoz, M., Reohr, W., Nassif, S., & Nowka, K.
(2009).
Statistical Yield Analysis of Silicon-On-Insulator Embedded DRAM. 190-194.
-
Wang, V., Agarwal, K., Nassif, S. R., Nowka, K. J., & Markovic, D.
(2009).
A Simplified Design Model for Random Process Variability. IEEE Transactions on Semiconductor Manufacturing.
12-21.
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Zhao, W., Liu, F., Agarwal, K., Acharyya, D., Nassif, S. R., Nowka, K. J., & Cao, Y. u.
(2009).
Rigorous Extraction of Process Variations for 65-nm CMOS Design. IEEE Transactions on Semiconductor Manufacturing.
196-203.
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Kim, K., Kuang, J. B., Gebara, F., Ngo, H. C., Chuang, C., & Nowka, K. J.
(2008).
Stable High-Density FD/SOI SRAM with Selective Back-Gate Bias Using Dual Buried Oxide. IEEE International SOI Conference.
37-+.
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Das, K., Bernstein, K., Burns, J., Gebara, F., Lo, S., Nowka, K., Rao, R., & Rosenfield, M.
(2008).
Variability and Power Management in sub-100nm SOI Technology for Reliable High Performance Systems. IEEE International SOI Conference.
1-4.
-
Nowka, K., Nassif, S., & Agarwal, K.
(2008).
Characterization and Design for Variability and Reliability. Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference.
341-346.
-
Datta, R., Abraham, J. A., Diril, A. U., Chatterjee, A., & Nowka, K. J.
(2008).
Performance-optimized design for parametric reliability. Journal of Electronic Testing.
129-141.
-
Wang, V., Agarwal, K., Nassif, S., Nowka, K., & Markovic, D.
(2008).
A Design Model for Random Process Variability. 734-737.
-
Wang, V., Agarwal, K., Nassif, S. R., Nowka, K. J., & Markovic, D.
(2008).
A Design Model for Random Process Variability. 734-737.
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Kuang, J. B., Mathews, A., Barth, J., Gebara, F., Nguyen, T., Schaub, J., ... Kirihata, T.
(2008).
An On-Chip Dual Supply Charge Pump System for 45nm PD SOI eDRAM. 66-69.
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Zhao, W., Cao, Y. u., Liu, F., Agarwal, K., Acharyya, D., Nassif, S., & Nowka, K.
(2007).
Rigorous extraction of process variations for 65nm CMOS design. European Solid-State Circuits Conference.
89-92.
-
Agarwal, K., & Nowka, K.
(2007).
Dynamic Power Management by Combination of Dual Static Supply Voltages. 1-5.
-
Nowka, K.
(2007).
Invited Talk 4. 1-1.
-
Agarwal, K., Nassif, S., Liu, F., Hayes, J., & Nowka, K.
(2007).
Rapid Characterization of Threshold Voltage Fluctuation in MOS Devices. 74-77.
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Gebara, F. H., Schaub, J. D., Nguyen, T. Y., Pea, J., Vo, I., Boerstier, D., & Nowka, K. J.
(2007).
A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology. Digest of technical papers / IEEE International Solid-State Circuits Conference. IEEE International Solid-State Circuits Conference.
312-313.
-
Zhao, W., Cao, Y. u., Liu, F., Agarwal, K., Acharyya, D., Nassif, S., & Nowka, K.
(2007).
Rigorous Extraction of Process Variations for 65nm CMOS Design. 89-92.
-
Deogun, H. S., Sylvester, D., & Nowka, K.
(2006).
Fine grained multi-threshold CMOS for enhanced leakage reduction. IEEE International Symposium on Circuits and Systems.
3850-3853.
-
Deogun, H. S., Senger, R., Sylvester, D., Brown, R., & Nowka, K.
(2006).
A dual-VDD boosted pulsed bus technique for low power and low leakage operation. Proceedings of the International Symposium on Low Power Electronics and Design.
73-78.
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Datta, R., Abraham, J. A., Diril, A. U., Chatterjee, A., & Nowka, K.
(2006).
Adaptive Design for Performance-Optimized Robustness**This work was supported in part by the IBM Faculty Partnership Award Program, and in part by the Gigascale Systems Research Center at UC Berkeley under contract 2003-DT-660 from Microelectronics Advanced Research Corporation (MARCO). Proceedings - IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems.
1-9.
-
Kim, K., Chuang, C., Kuang, J. B., Ngo, R. C., & Nowka, K. J.
(2006).
Back-Gate Controlled Wide Tunable Range Diode Voltage in Asymmetrical Double-Gate Devices. IEEE International SOI Conference.
151-152.
-
Datta, R., Montoye, R., Nowka, K., Sawada, J., & Abraham, J. A.
(2006).
Design of Shifting and Permutation Units using LSDL Circuit Family. Conference record / Asilomar Conference on Signals, Systems & Computers. Asilomar Conference on Signals, Systems & Computers.
1692-1696.
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Ngo, H., Kim, K., Chuang, C., Kuang, J. B., Gebara, F., & Nowka, K.
(2006).
An Asymmetrical Double-Gate VCO with Wide Frequency Range. International Symposium on Vlsi Technology Systems and Applications.
1-2.
-
Datta, R., Carpenter, G., Nowka, K., & Abraham, J. A.
(2006).
A Scheme for On-Chip Timing Characterization* *This work was supported in part by the Gigascale Systems Research Center at UC Berkeley under contract 2003-DT-660 from Microelectronics Advanced Research Corporation(MARCO). 1-6.
-
Agarwal, K., Liu, F., McDowell, C., Nassif, S., Nowka, K., Palmer, M., Acharyya, D., & Plusquellic, J.
(2006).
A Test Structure for Characterizing Local Device Mismatches. 67-68.
-
Yu, X. Y., Montoye, R., Nowka, K., Zeydel, B., & Oklobdzija, V.
(2006).
Circuit Design Style for Energy Efficiency: LSDL and Compound Domino. Lecture Notes in Computer Science.
47-55.
-
Deogun, H. S., Sylvester, D., & Nowka, K.
(2006).
Fine grained multi-threshold CMOS for enhanced leakage reduction. IEEE International Symposium on Circuits and Systems proceedings. IEEE International Symposium on Circuits and Systems.
4-pp..
-
Agarwal, K., Nowka, K., Deogun, H., & Sylvester, D.
(2006).
Power Gating with Multiple Sleep Modes. Proceedings - International Symposium on Quality Electronic Design, ISQED.
633-637.
-
Elakkumanan, P., Kuang, J. B., Nowka, K., Sridhar, R., Kanj, R., & Nassif, S.
(2006).
SRAM Local Bit Line Access Failure Analyses. Proceedings - International Symposium on Quality Electronic Design, ISQED.
204-209.
-
Kuang, J. B., Ngo, H. C., Nowka, K. J., Ehrenreich, S., Drake, A. J., Pille, J., ... Vo, I.
(2006).
The design and implementation of a low-overhead supply-gated SRAM. European Solid-State Circuits Conference.
287-+.
-
Nowka, K.
(2005).
Circuit Design for Low Power. 1-49.
-
Gebara, F. H., Schaub, J. D., Drake, A. J., Nowka, K. J., & Brown, R. B.
(2005).
4.0GHz 0.18m CMOS PLL based on an interpolative oscillator. 2007 IEEE Symposium on VLSI Circuits.
100-103.
-
Kuang, J. B., Ngo, H. C., Nowka, K. J., Law, J. C., & Joshi, R. V.
(2005).
A low-overhead virtual rail technique for SRAM leakage power reduction. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
574-579.
-
Deogun, H. S., Rao, R., Sylvester, D., & Nowka, K.
(2005).
Adaptive MTCMOS for Dynamic Leakage and Frequency Control using Variable Footer Strength. 147-150.
-
Sivagnaname, J., Ngo, H. C., Nowka, K. J., Montoye, R. K., & Brown, R. B.
(2005).
Controlled-load limited switch dynamic logic circuit. Proceedings - International Symposium on Quality Electronic Design, ISQED.
83-87.
-
Kuang, J. B., Kim, K., Chuang, C. T., Ngo, H. C., & Nowka, K. J.
(2005).
Dynamic circuit techniques using independently controlled double-gate devices. IEEE International SOI Conference.
74-76.
-
Deogun, H. S., Rao, R., Sylvester, D., Brown, R., & Nowka, K.
(2005).
Dynamically Pulsed MTCMOS with Bus Encoding for Total Power and Crosstalk Minimization. Proceedings - International Symposium on Quality Electronic Design, ISQED.
88-93.
-
Rao, R., Agarwal, K., Devgan, A., Nowka, K., Sylvester, D., & Brown, R.
(2005).
Parametric Yield Analysis and Constrained-Based Supply Voltage Optimization. Proceedings - International Symposium on Quality Electronic Design, ISQED.
284-290.
-
Sivagnaname, J., Ngo, H. C., Nowka, K. J., Montoye, R. K., & Brown, R. B.
(2005).
Wide limited switch dynamic logic circuit implementations. Proceedings of the IEEE International Conference on VLSI Design.
94-99.
-
Drake, A. J., Nowka, K. J., Nguyen, T. Y., Burns, J. L., & Brown, R. B.
(2004).
Resonant clocking using distributed parasitic capacitance. IEEE Journal of Solid-State Circuits.
1520-1528.
-
Rao, R., Agarwal, K., Sylvester, D., Brown, R., Nowka, K., & Nassif, S.
(2004).
Approaches to run-time and standby mode leakage reduction in global buses. 188-193.
-
Carballo, J. A., Nowka, K., Yoo, S., Vo, I., Cranford, C., & Norman, R.
(2004).
Requirement-based design methods for adaptive communications links. Design Automation Conference.
93-98.
-
Datta, R., Abraham, J. A., Montoye, R., Belluomini, W., Ngo, H., McDowell, C., Kuang, J. B., & Nowka, K.
(2004).
A low latency and low power dynamic Carry Save Adder. IEEE International Symposium on Circuits and Systems.
ii-477.
-
Datta, R., Abraham, J. A., Montoye, R. K., Belluomini, W., Ngo, H. C., McDowell, C., Kuang, J. B., & Nowka, K. J.
(2004).
A low latency and low power dynamic Carry Save Adder. 477-480.
-
Gebara, F. H., Martin, S. M., Nowka, K., & Brown, R. B.
(2004).
Accurate Current Mirroring in the Presence of Gate Leakage Current. IEEE International SOI Conference.
117-118.
-
Rao, R., Agarwal, K., Sylvester, D., Brown, R., Nowka, K., & Nassif, S.
(2004).
Approaches to Run-Time and Standby Mode Leakage Reduction in Global Buses. Proceedings of the International Symposium on Low Power Electronics and Design.
188-193.
-
Drake, A. J., Zamdmer, N., Nowka, K. J., & Brown, R. B.
(2003).
Analysis of the impact of gate-body signal phase on DTMOS inverters in 0.13m PD-SOI. 99-100.
-
Drake, A. J., Nowka, K. J., & Brown, R. B.
(2003).
Evaluation of Dynamic-Threshold Logic for Low-Power VLSI Design in 0.13um PD-SOI. 263-263.
-
Drake, A. J., Nowka, K. J., Nguyen, T. Y., Burns, J. L., & Brown, R. B.
(2003).
Resonant clocking using distributed parasitic capacitance. Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference.
647-650.
-
Nowka, K., Carpenter, G., Mac Donald, E., Ngo, H., Brock, B., Ishil, K., Nguyen, T., & Burns, J.
(2002).
A 0.9 V to 1.95 V dynamic voltage-scalable and frequency-scalable 32 b PowerPC processor. Digest of technical papers / IEEE International Solid-State Circuits Conference. IEEE International Solid-State Circuits Conference.
340-341+333.
-
Nowka, K., Carpenter, G., Donald, E. M., Ngo, H., Brock, B., Ishii, K., Nguyen, T., & Burns, J.
(2002).
A 0.9V to 1.95V dynamic voltage-scalable and frequency-scalable 32b powerPC processor. Digest of technical papers / IEEE International Solid-State Circuits Conference. IEEE International Solid-State Circuits Conference.
272-503.
-
Kwon, O., Swartzlander, E. E., & Nowka, K.
(2001).
A fast hybrid carry-lookahead/carry-select adder design. Proceedings of the IEEE Great Lakes Symposium on VLSI.
149-152.
-
Dao, H. Q., Nowka, K., & Oklobdzija, V.
(2001).
Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation. 56-59.
-
Schmookler, M. S., & Nowka, K. J.
(2001).
Leading zero anticipation and detection - A comparison of methods. ARITH-15 2001: 15TH SYMPOSIUM ON COMPUTER ARITHMETIC, PROCEEDINGS.
7-12.
-
Posluszny, S., Aoki, N., Boerstler, D., Coulman, P., Dhong, S., Flachs, B., ... Villarrubial, P.
(2000).
"Timing closure by design," a high frequency microprocessor design methodology. Design Automation Conference.
712-717.
-
Lee, K. T., & Nowka, K. J.
(2000).
1 GHz leading zero anticipator using independent sign-bit determination logic. 194-195.
-
Hofstee, P., Aoki, N., Boerstler, D., Coulman, P., Dhong, S., Flachs, B., ... Weinberger, B.
(2000).
A 1 GHz single-issue 64 b PowerPC processor. Digest of technical papers / IEEE International Solid-State Circuits Conference. IEEE International Solid-State Circuits Conference.
92-93.
-
Kwon, O., Nowka, K., & Swartzlander, E. E.
(2000).
A 16-bit/spl times/16-bit MAC design using fast 5:2 compressors. IEEE 17TH INTERNATIONAL CONFERENCE ON APPLICATION-SPECIFIC SYSTEMS, ARCHITECTURES AND PROCESSORS, PROCEEDINGS.
235-243.
-
Hofstee, H. P., & Nowka, K. J.
(1999).
Beyond 1 GHz. Proceedings of the ... Custom Integrated Circuits Conference. Custom Integrated Circuits Conference.
57-61.
-
Silberman, J., Aoki, N., Boerstler, D., Burns, J., Dhong, S., Essbaum, A., ... Zoric, B.
(1998).
A 1.0 GHz single-issue 64 b powerPC integer processor. Digest of technical papers / IEEE International Solid-State Circuits Conference. IEEE International Solid-State Circuits Conference.
230-231.
-
Nowka, K. J., & Galambos, T.
(1998).
Circuit design techniques for a gigahertz integer microprocessor. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
11-16.
-
Posluszny, S., Aoki, N., Boerstler, D., Burns, J., Dhong, S., Ghoshal, U., ... Vo, I.
(1998).
Design methodology for a 1.0 GHz microprocessor. IEEE International Conference on Computer Design - VLSI in Computers and Processors.
17-23.
-
Heidel, D., Dhong, S., Hofstee, P., Immediato, M., Nowka, K., Silberman, J., & Stawiasz, K.
(1998).
High speed serializing/de-serializing design-for-test method for evaluating a 1 GHz microprocessor. 234-238.
-
Burns, J. L., & Nowka, K. J.
(1998).
Parallel condition-code generation for high-frequency PowerPC microprocessors. 112-115.
-
Nowka, K. J., & Hofstee, H. P.
(1997).
Circuits and microarchitecture for gigahertz VLSI designs. 284-287.
-
NOWKA, K. J., & FLYNN, M. J.
(1995).
System design using wave-pipelining: A CMOS VLSI vector unit. 1995 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-3.
2301-2304.
-
Flynn, M. J., Nowka, K., Bewick, G., Schwarz, E., & Quach, N.
(1995).
The SNAP project: towards sub-nanosecond arithmetic. 75-82.
-
Zhal, L., Bhandri, M., Um, D., Nowka, K., Landivar, J., & Ladivar, J. L.
(2023).
Plant Height Estimation using Satellite/UAV Data Fusion and Machine Learning. 314-1-314-2.
-
institutional repository document
-
Gadepally, K. C., Dhal, S. B., Kalafatis, S., & Nowka, K.
(2023).
Systematic Model Complexity Reduction by Elimination of Irrelevant Layers in Convolutional Neural Networks
-
Dhal, S. B., Jain, S., Gadepally, K. C., Vijaykumar, P., Sharma, B. H., Acharya, B. S., Nowka, K., & Kalafatis, S.
(2023).
Predicting Large Wildfires in the Contiguous United States Using Deep Neural Networks
-
Dhal, S. B., Bhandari, M., Gadepally, K. C., Acharya, B. S., Pal, P., Landivar, J., ... Kalafatis, S.
(2023).
In-Season Growth Forecasting in Cotton Using Unmanned Aerial System- based Canopy Attributes and LSTM Models
-
Gadepally, K. C., Dhal, S. B., Kalafatis, S., & Nowka, K.
(2023).
Privacy First Path Analysis Using Clickstream Data
-
Gadepally, K. C., Dhal, S. B., Kalafatis, S., & Nowka, K.
(2023).
Systematic Model Complexity Reduction by Elimination of Irrelevant Layers in Convolutional Neural Networks
Teaching
teaching activities
- ECEN214 Elec Circuit Theory Instructor
- ECEN215 Prin Of Electrical Engr Instructor
- ECEN250 Machine Learning Elen Instructor
- ECEN289 Sptp: Machine Learning Elen Instructor
- ECEN360 Computational Data Science Instructor
- ECEN403 Electrical Design Lab I Instructor
- ECEN403 Electrical Design Lab I Instructor
- ECEN404 Electrical Design Lab Ii Instructor
- ECEN485 Directed Studies Instructor
- ECEN489 Sptp: Ai Tech Apps Instructor
- ECEN491 Hnr-research Instructor
- ECEN684 Professional Internship Instructor
- ECEN691 Research Instructor
- STAT315 Computational Data Science Instructor
Works By Students
chaired theses and dissertations
-
Gadepally, Krishna Chaitanya (2023-05). Techniques and Methods for Improved Effectiveness and Accuracy in Computer Vision Applications.
-
Lopez Carrasco, Cesar Ramon (2020-12). Scalable Systolic Array Architecture (SSAA) - A General Convolutional Neural Network ISA and Compiler-Enabled Dataflow to Maximize Parallelism While Reducing Memory Utilization.
Background
education and training
- Ph.D. in Electrical Engineering, Stanford University - (Stanford, California, United States) 1995
- M.S. in Electrical Engineering, Stanford University - (Stanford, California, United States) 1988
- B.S. in Computer Engineering, Iowa State University - (Ames, Iowa, United States) 1986
Contact
first name
- Kevin
has last name
- Nowka
Other
- kjnowka@tamu.edu