A 16-Bit by 16-Bit MAC Design Using Fast 5:3 Compressor Cells Academic Article uri icon

abstract

  • 3:2 counters and 4:2 compressors have been widely used for multiplier implementations. In this paper, a fast 5:3 compressor is derived for high-speed multiplier implementations. The fast 5:3 compression is obtained by applying two rows of fast 2-bit adder cells to five rows in a partial product matrix. As a design example, a 16-bit by 16-bit MAC (Multiply and Accumulate) design is investigated both in a purely logical gate implementation and in a highly customized design. For the partial product reduction, the use of the new 5:3 compression leads to 14.3% speed improvement in terms of XOR gate delay. In a dynamic CMOS circuit implementation using 0.225 m bulk CMOS technology, 11.7% speed improvement is observed with 8.1% less power consumption for the reduction tree.

published proceedings

  • Journal of Signal Processing Systems

author list (cited authors)

  • Kwon, O., Nowka, K., & Swartzlander, E. E.

citation count

  • 42

complete list of authors

  • Kwon, Ohsang||Nowka, Kevin||Swartzlander, Earl E

publication date

  • June 2002