1 GHz leading zero anticipator using independent sign-bit determination logic Conference Paper

abstract

• The architecture and design methodology of a leading zero anticipator (LZA) using built-in sign-bit determination logic are described. The LZA was implemented in the 1 GHz floating point unit using a 1.8 V, 0.12/0.15 (n/p)m L eff . IBM CMOS technology. The design shows 730 ps of latency and operates at 1 GHz with 5 levels of delayed reset dynamic circuit logic. With the LZA the sign-bit is determined in 446 ps with an area overhead of 8%, whereas a conventional adder generates the sign-bit in 770 ps.

name of conference

• 2000 Symposium on VLSI Circuits. Digest of Technical Papers (Cat. No.00CH37103)

authors

• Nowka, Kevin

published proceedings

• 2000 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS

author list (cited authors)

• Lee, K. T., & Nowka, K. J.

citation count

• 15

complete list of authors

• Lee, KT||Nowka, KJ

publication date

• January 2000

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

keywords

• 40 Engineering
• 4008 Electrical Engineering
• 4009 Electronics, Sensors And Digital Hardware

Digital Object Identifier (DOI)

• 10.1109/VLSIC.2000.852888

International Standard Book Number (ISBN) 10

• 0-7803-6310-8

start page

• 194

end page

• 195

URL

• http://dx.doi.org/10.1109/vlsic.2000.852888