A 32nm 0.5V-Supply Dual-Read 6T SRAM Conference Paper uri icon

abstract

  • Dual read port SRAMs play a critical role in high performance cache designs, but stability and sensing challenges typically limit the low voltage operation. We report a high-performance dual read port 8-way set associative 6T SRAM with a one clock cycle access latency, in a 32nm metal-gate partially depleted (PD) SOI technology, for low-voltage applications. Hardware exhibits robust operation at 348MHz and 0.5V with a read and write power of 3.33 and 1.97mW, respectively, per 4.5KB active array with both read ports accessed at the highest activity data pattern. At a 0.6V supply, an access speed of 1.2GHz is observed. 2010 IEEE.

name of conference

  • IEEE Custom Integrated Circuits Conference 2010

published proceedings

  • IEEE CUSTOM INTEGRATED CIRCUITS CONFERENCE 2010

author list (cited authors)

  • Kuang, J. B., Schaub, J. D., Gebara, F. H., Wendel, D., Saroop, S., Nguyen, T., ... Nowka, K. J.

citation count

  • 0

complete list of authors

  • Kuang, JB||Schaub, JD||Gebara, FH||Wendel, D||Saroop, S||Nguyen, T||Froehnel, T||Mueller, A||Durham, CM||Sautter, R||Lloyd, B||Robbins, B||Pille, J||Nassif, SR||Nowka, KJ

editor list (cited editors)

  • Snyder, J., Patel, R., & Andre, T.

publication date

  • September 2010