TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell With Improved Stability Academic Article

abstract

• This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area penalty. The scheme improves 6T SRAM standby leakage, read stability, write ability, and read/write performance. The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies. Numerical 2-D mixed-mode device/circuit simulation results validate the merits and advantages of the proposed scheme. 2009 IEEE.

authors

• Nowka, Kevin

published proceedings

• IEEE TRANSACTIONS ON ELECTRON DEVICES

author list (cited authors)

• Kim, K., Kuang, J. B., Gebara, F. H., Ngo, H. C., Chuang, C., & Nowka, K. J.

citation count

• 6

complete list of authors

• Kim, Keunwoo||Kuang, Jente B||Gebara, Fadi H||Ngo, Hung C||Chuang, Ching-Te||Nowka, Kevin J

publication date

• December 2009

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Transactions on Electron Devices  Journal

keywords

• Fd/soi Device
• Mix-mode Simulator
• Read Stability
• Substrate Bias

Digital Object Identifier (DOI)

• 10.1109/TED.2009.2030657

start page

• 3033

end page

• 3040

volume

• 56

issue

• 12

URL

• http://dx.doi.org/10.1109/ted.2009.2030657