TCAD/Physics-Based Analysis of High-Density Dual-BOX FD/SOI SRAM Cell with Improved Stability Academic Article uri icon


  • This paper presents a new SRAM cell using a global back-gate bias scheme in dual buried-oxide (BOX) FD/SOI CMOS technologies. The scheme uses a single global back-gate bias for all cells in the entire columns or subarray, thereby reducing the area penalty. The scheme improves 6T SRAM standby leakage, read stability, write ability, and read/write performance. The basic concept of the proposed scheme is discussed based on physical analysis/equation to facilitate device parameter optimization for SRAM cell design in back-gated FD/SOI technologies. Numerical 2-D mixed-mode device/circuit simulation results validate the merits and advantages of the proposed scheme. © 2009 IEEE.

author list (cited authors)

  • Kim, K., Kuang, J. B., Gebara, F. H., Ngo, H. C., Chuang, C., & Nowka, K. J.

publication date

  • January 1, 2009 11:11 AM