Low-Power High-Performance Asymmetrical Double-Gate Circuits Using Back-Gate-Controlled Wide-Tunable-Range Diode Voltage Academic Article uri icon

abstract

  • This paper presents a new power-reduction scheme using a back-gate-controlled asymmetrical double-gate device with robust data-retention capability for high-performance logic/SRAM power gating or variable/dynamic supply applications. The scheme reduces the transistor count, area, and capacitance in the header/footer device and provides a wide range of virtual ground (GND) or supply voltage. Physical analysis and numerical mix-mode device/circuit-simulation results confirm that the proposed scheme can be applied to low-power high-performance circuit applications in 65-nm technology node and beyond. Variable/dynamic supply or GND voltage using the proposed scheme improves read and write margins in scaled SRAM without degrading read and write performance. © 2007 IEEE.

author list (cited authors)

  • Kim, K., Chuang, C., Kuang, J. B., Ngo, H. C., & Nowka, K. J.

citation count

  • 3

publication date

  • September 2007