A 1 GHz single-issue 64 b PowerPC processor Conference Paper

abstract

• A 64b 1 GHz single-issue PowerPC processor containing 19M transistors was studied. The microprocessor was fabricated on a 0.12 m six-layer copper interconnect complementary metal oxide semiconductor (CMOS). The processor was implemented using delayed-reset and self-resetting dynamic circuit macros. The new features in the chip included fully pipelined floating-point unit (FPU), sum-addressed memory management units (MMU), improved clock generation and distribution and microarchitecture and floorplan to balance critical paths.

name of conference

• 2000 IEEE International Solid-State Circuits Conference. Digest of Technical Papers (Cat. No.00CH37056)

authors

• Nowka, Kevin

published proceedings

• 2012 IEEE International Solid-State Circuits Conference
• Digest of Technical Papers - IEEE International Solid-State Circuits Conference

author list (cited authors)

• Hofstee, P., Aoki, N., Boerstler, D., Coulman, P., Dhong, S., Flachs, B., ... Weinberger, B.

citation count

• 37

complete list of authors

• Hofstee, P||Aoki, N||Boerstler, D||Coulman, P||Dhong, S||Flachs, B||Kojima, N||Kwon, O||Lee, K||Meltzer, D||Nowka, K||Park, J||Peter, J||Posluszny, S||Shapiro, M||Silberman, J||Takahashi, O||Weinberger, B

publication date

• January 2000

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• Digest of technical papers / IEEE International Solid-State Circuits Conference. IEEE International Solid-State Circuits Conference  Journal

keywords

• 40 Engineering
• 4008 Electrical Engineering
• 4009 Electronics, Sensors And Digital Hardware

Digital Object Identifier (DOI)

• 10.1109/isscc.2000.839705

start page

• 92

end page

• 93

URL

• http://dx.doi.org/10.1109/isscc.2000.839705