In-situ Measurement of Variability in 45-nm SOI Embedded DRAM Arrays Conference Paper

abstract

• A technique for in-situ measurement of process variation in deep trench capacitance, bitline capacitance, and device threshold voltage in embedded DRAM arrays is presented. The technique is used to directly measure the parameter statistics in two product representative 45-nm SOI eDRAM arrays. 2010 IEEE.

name of conference

• 2010 Symposium on VLSI Circuits

authors

• Nowka, Kevin

published proceedings

• 2010 Symposium on VLSI Circuits

author list (cited authors)

• Agarwal, K., Hayes, J., Barth, J., Jacunski, M., Nowka, K., Kirihata, T., & Iyer, S.

citation count

• 3

complete list of authors

• Agarwal, Kanak||Hayes, Jerry||Barth, John||Jacunski, Mark||Nowka, Kevin||Kirihata, Toshiaki||Iyer, Subramanian

publication date

• June 2010

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

keywords

• 40 Engineering
• 4008 Electrical Engineering

Digital Object Identifier (DOI)

• 10.1109/vlsic.2010.5560302

International Standard Book Number (ISBN) 13

• 9781424476367

start page

• 189

end page

• 190

volume

• 1

URL

• http://dx.doi.org/10.1109/vlsic.2010.5560302