Statistical Yield Analysis of Silicon-On-Insulator Embedded DRAM Conference Paper uri icon

abstract

  • We study the yield of a 65nm SOl eDRAM design. The impact of random dopant fluctuations in the cell and micro sense amp is studied under different systematic comer and device type considerations. Trench capacitor variation effects and yield timing windows are evaluated. By analyzing the circuit hierarchy, we are able to understand yield trends and hence suitable design guidelines. For the first time a fast montecarlo statistical analysis approach is employed for eDRAM analysis. For this, we rely on a well-developed SRAM statistical yield analysis methodology. It is shown that a multiplicity of devices and design considerations can be critical based on the memory operating comers and conditions. It is also shown that high vt sense amp devices, unlike low Vt devices, enable sufficient design yield windows. 2009 IEEE.

name of conference

  • 2009 10th International Symposium on Quality of Electronic Design

published proceedings

  • 2009 10th International Symposium on Quality of Electronic Design

author list (cited authors)

  • Kanj, R., Joshi, R., Kuang, J. B., Kim, J., Meterelliyoz, M., Reohr, W., Nassif, S., & Nowka, K.

citation count

  • 2

complete list of authors

  • Kanj, R||Joshi, R||Kuang, JB||Kim, J||Meterelliyoz, M||Reohr, W||Nassif, S||Nowka, K

publication date

  • March 2009