Analysis of clocked timing elements for dynamic voltage scaling effects over process parameter variation Conference Paper uri icon

abstract

  • In power-constrained systems, the power efficiency of latches and flip-flops is pivotal. Characteristics of three selected latches and FFs were analyzed for their behavior under voltage scaling and different process corners in a O.18um CMOS technology. The relative performance amongst the latches/FFs was consistent across the different supply voltages. At low-voltage power-delay-product was degraded by about 25%. Energy-delay-product was approximately doubled at low-voltage - for all latches/FFs over all process corners. This result was smaller in comparison to the ideal voltage scaling characteristics mainly because the effects of velocity saturation were less severe at low voltage. All three designs suffered more due to process variation under low-voltage conditions.

name of conference

  • Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01

published proceedings

  • Proceedings of the 2001 international symposium on Low power electronics and design - ISLPED '01
  • Proceedings of the International Symposium on Low Power Electronics and Design, Digest of Technical Papers

author list (cited authors)

  • Dao, H. Q., Nowka, K., & Oklobdzija, V.

citation count

  • 10

complete list of authors

  • Dao, Hoang Q||Nowka, Kevin||Oklobdzija, Vojin

editor list (cited editors)

  • Macii, E., De, V., & Irwin, M. J.

publication date

  • January 2001