A 16-bit/spl times/16-bit MAC design using fast 5:2 compressors Conference Paper uri icon

abstract

  • 3.2 counters and/or 4:2 compressors have been widely used for multiplier implementations. In this paper, a new logical decomposition is derived for fast 5:2 compressor and is proposed to be used for 16-bit 16-bit MAC designs. In addition, when the accumulator output is in carry-save form, one row in partial product matrix can be eliminated prior to the partial product reduction process. These new methods are combined and explained with 16-bit 16-bit 2's complement MAC(multiply and accumulate) designs. The use of the new 5:2 compressor leads to 14% speed improvement in the MAC design over the conventional designs using 4:2 compressors and 3:2 counters.

name of conference

  • Proceedings IEEE International Conference on Application-Specific Systems, Architectures, and Processors

published proceedings

  • 2013 IEEE 24th International Conference on Application-Specific Systems, Architectures and Processors
  • Proceedings of the International Conference on Application-Specific Systems, Architectures and Processors

author list (cited authors)

  • Kwon, O., Nowka, K., & Swartzlander, E. E.

citation count

  • 26

complete list of authors

  • Kwon, Ohsang||Nowka, K||Swartzlander, EE

publication date

  • January 2000