A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology
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abstract
Two PLLs were designed using current-steering interpolating ring oscillators. The regular-V, PLL demonstrates a 3.2 lock range and a maximum frequency of 24.6GHz with 1.28psrms jitter at 1V. The high-Vt PLL exhibits a 3.5 lock range at 6% lower frequency. The 0.18mm2 PLLs consume 16mW of power from 1V and are fabricated in a PD-SOI 65nm technology. 2007 IEEE.
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2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers