A 1V 18GHz Clock Generator in a 65nm PD-SOI Technology Conference Paper uri icon

abstract

  • Two PLLs were designed using current-steering interpolating ring oscillators. The regular-V, PLL demonstrates a 3.2 lock range and a maximum frequency of 24.6GHz with 1.28psrms jitter at 1V. The high-Vt PLL exhibits a 3.5 lock range at 6% lower frequency. The 0.18mm2 PLLs consume 16mW of power from 1V and are fabricated in a PD-SOI 65nm technology. 2007 IEEE.

name of conference

  • 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

published proceedings

  • 2007 IEEE International Solid-State Circuits Conference. Digest of Technical Papers

author list (cited authors)

  • Gebara, F. H., Schaub, J. D., Nguyen, T. Y., Pea, J., Vo, I., Boerstier, D., & Nowka, K. J.

citation count

  • 0

complete list of authors

  • Gebara, Fadi H||Schaub, Jeremy D||Nguyen, Tuyet Y||Peña, Jarom||Vo, Ivan||Boerstier, David||Nowka, Kevin J

publication date

  • February 2007