Parallel condition-code generation for high-frequency PowerPC microprocessors Conference Paper

abstract

• Improving the speed and performance of microprocessors requires aggressive leveraging of the interplay of microarchitecture and circuit design. We describe a unique, high-frequency dataflow macro for accelerating conditional-branch resolution by computing condition codes in parallel with computing the corresponding arithmetic results. This macro improves the microarchitecture by reducing conditional-branch latency while achieving high speed through a pulse-mode, delayed-reset dynamic circuit implementation. The design has been realized in a 64-bit PowerPC integer processor that operates at 1.0 GHz (0.15 micron CMOS process).

authors

• Nowka, Kevin

published proceedings

• IEEE Symposium on VLSI Circuits, Digest of Technical Papers

author list (cited authors)

• Burns, J. L., & Nowka, K. J.

complete list of authors

• Burns, JL||Nowka, KJ

publication date

• January 1998

start page

• 112

end page

• 115