A 1.0-GHz single-issue 64-bit powerPC integer processor Academic Article

abstract

• The organization and circuit design of a 1.0-GHz integer processor built in 0.25-m CMOS technology are presented. A microarchitecture emphasizing parallel computation with a single late select per cycle, structured control logic implemented by read-only-memories and programmable logic arrays, and a delayed reset dynamic circuit style enabling complex functions to be implemented in a few levels of logic are among the key design choices described. A means for at-speed scan testing of this high-frequency processor by a low-speed tester is also presented.

authors

• Nowka, Kevin

published proceedings

• IEEE Journal of Solid-State Circuits

altmetric score

• 3

author list (cited authors)

• Silberman, J., Aoki, N., Boerstler, D., Burns, J. L., Dhong, S., Essbaum, A., ... Zoric, B.

citation count

• 44

complete list of authors

• Silberman, J||Aoki, N||Boerstler, D||Burns, JL||Dhong, Sang||Essbaum, A||Ghoshal, U||Heidel, D||Hofstee, P||Lee, Kyung Tek||Meltzer, D||Ngo, Hung||Nowka, K||Posluszny, S||Takahashi, O||Vo, I||Zoric, B

publication date

• November 1998

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Journal of Solid-State Circuits  Journal

keywords

• 40 Engineering
• 4008 Electrical Engineering
• 4009 Electronics, Sensors And Digital Hardware

Digital Object Identifier (DOI)

• 10.1109/4.726542

start page

• 1600

end page

• 1608

volume

• 33

issue

• 11

URL

• http://dx.doi.org/10.1109/4.726542