publication venue for
- A Jitter-Robust 40 Gb/s ADC-Based Multicarrier Receiver Front-End With 4-GS/s Baseband Pipeline-SAR ADCs in 22-nm FinFET. 58:662-676. 2023
- A 1.41-pJ/b 224-Gb/s PAM4 6-bit ADC-Based SerDes Receiver With Hybrid AFE Capable of Supporting Long Reach Channels. 58:8-18. 2023
- A 32-Gb/s Simultaneous Bidirectional Source-Synchronous Transceiver With Adaptive Echo Cancellation Techniques. 55:439-451. 2020
- A 52-Gb/s ADC-Based PAM-4 Receiver With Comparator-Assisted 2-bit/Stage SAR ADC and Partially Unrolled DFE in 65-nm CMOS. 54:659-671. 2019
- A 56-Gb/s PAM4 Receiver With Low-Overhead Techniques for Threshold and Edge-Based DFE FIR-and IIR-Tap Adaptation in 65-nm CMOS. 54:672-684. 2019
- Introduction to the Special Section on the 2018 Custom Integrated Circuits Conference. 54:611-612. 2019
- A 44-fJ/Conversion Step 200-MS/s Pipeline ADC Employing Current-Mode MDACs. 53:3280-3292. 2018
- A Fully On-Chip 80-pJ/b OOK Super-Regenerative Receiver With Sensitivity-Data Rate Tradeoff Capability. 53:1443-1456. 2018
- Guest Editorial 2017 IEEE Custom Integrated Circuits Conference. 53:679-680. 2018
- A Reconfigurable 16/32 Gb/s Dual-Mode NRZ/PAM4 SerDes in 65-nm CMOS. 52:2430-2447. 2017
- A 25 GS/s 6b TI Two-Stage Multi-Bit Search ADC With Soft-Decision Selection Algorithm in 65 nm CMOS. 52:2168-2179. 2017
- A Low-Power Digitizer for Back-Illuminated 3-D-Stacked CMOS Image Sensor Readout With Passing Window and Double Auto-Zeroing Techniques. 52:1591-1604. 2017
- A 25 Gb/s Hybrid-Integrated Silicon Photonic Source-Synchronous Receiver With Microring Wavelength Stabilization. 51:2129-2141. 2016
- A 10 Gb/s Hybrid ADC-Based Receiver With Embedded Analog and Per-Symbol Dynamically Enabled Digital Equalization. 51:671-685. 2016
- A 35 dBm Output Power and 38 dB Linear Gain PA With 44.9% Peak PAE at 1.9 GHz in 40 nm CMOS. 51:587-597. 2016
- A 6 bit 10 GS/s TI-SAR ADC With Low-Overhead Embedded FFE/DFE Equalization for Wireline Receiver Applications. 49:2560-2574. 2014
- An 8-16 Gb/s, 0.65-1.05 pJ/b, Voltage-Mode Transmitter With Analog Impedance Modulation Equalization and Sub-3 ns Power-State Transitioning. 49:2631-2643. 2014
- Silicon Photonic Transceiver Circuits With Microring Resonator Bias-Based Wavelength Stabilization in 65 nm CMOS. 49:1419-1436. 2014
- External Capacitor-Less Low Drop-Out Regulator with 25 dB Superior Power Supply Rejection in the 0.44 MHz Range. 49:486-501. 2014
- A Power-Efficient Wireless System With Adaptive Supply Control for Deep Brain Stimulation.. 48:2203-2216. 2013
- A 6-b 1.6-GS/s ADC With Redundant Cycle One-Tap Embedded DFE in 90-nm CMOS. 48:1885-1897. 2013
- A 0.470.66 pJ/bit, 4.88 Gb/s I/O Transceiver in 65 nm CMOS. 48:1276-1289. 2013
- A Low-Power 26-GHz Transformer-Based Regulated Cascode SiGe BiCMOS Transimpedance Amplifier. 48:1264-1275. 2013
- A 2-GHz Highly Linear Efficient Dual-Mode BiCMOS Power Amplifier Using a Reconfigurable Matching Network. 47:2385-2404. 2012
- 0.16-0.25 pJ/bit, 8 Gb/s Near-Threshold Serial Link Receiver With Super-Harmonic Injection-Locking. 47:1842-1853. 2012
- An Inductor-Less Noise-Cancelling Broadband Low Noise Amplifier With Composite Transistor Pair in 90 nm CMOS Technology. 46:1111-1122. 2011
- A Continuous Time Multi-Bit $Delta Sigma$ ADC Using Time Domain Quantizer and Feedback Element. 46:639-650. 2011
- A Sixth-Order 200 MHz IF Bandpass Sigma-Delta Modulator With Over 68 dB SNDR in 10 MHz Bandwidth. 45:1122-1136. 2010
- High PSR Low Drop-Out Regulator With Feed-Forward Ripple Cancellation Technique. 45:565-577. 2010
- A Millimeter-Wave (23-32 GHz) Wideband BiCMOS Low-Noise Amplifier. 45:289-299. 2010
- The Recycling Folded Cascode: A General Enhancement of the Folded Cascode Amplifier. 44:2535-2542. 2009
- A CMOS 1 Gb/s 5-Tap Fractionally-Spaced Equalizer. 43:2482-2491. 2008
- A 63 dB SNR, 75-mW Bandpass RF $SigmaDelta$ ADC at 950 MHz Using 3.8-GHz Clock in 0.25-$mu{hbox {m}}$ SiGe BiCMOS Technology. 42:269-279. 2007
- A High Dynamic Range CMOS Variable Gain Amplifier for Mobile DTV Tuner. 42:292-301. 2007
- Continuous-Time Common-Mode Feedback for High-Speed Switched-Capacitor Networks. 40:1610-1617. 2005
- Low-Voltage Low-Power Lvds Drivers. 40:472-479. 2005
-
A 2-${hbox{V}}_{
m pp}$ 80200-MHz Fourth-Order Continuous-Time Linear Phase Filter With Automatic Frequency Tuning. 38:1745-1749. 2003 - A 3.3-V CMOS adaptive analog video line driver with low distortion performance. 38:1051-1058. 2003
- Compact Sub-Hertz OTA-C Filter Design With Interface-Trap Charge Pump. 38:929-934. 2003
- An Enhanced Adaptive $Q$-Tuning Scheme for a 100-Mhz Fully Symmetric OTA-Based Bandpass Filter. 38:585-593. 2003
- A 60-mW 200-MHz Continuous-Time Seventh-Order Linear Phase Filter With On-Chip Automatic Tuning System. 38:216-225. 2003
- A Robust Feedforward Compensation Scheme for Multistage Operational Transconductance Amplifiers with No Miller Capacitors. 38:237-243. 2003
- An enhanced adaptive Q-tuning scheme for a 100-MHz fully symmetric OTA based bandpass filter. 38:585-593. 2003
- A 32-bit PowerPC system-on-a-chip with support for dynamic voltage scaling and dynamic frequency scaling. 37:1441-1447. 2002
- A 1.0-GHz single-issue 64-bit powerPC integer processor. 33:1600-1608. 1998
- Design techniques for high-performance full-CMOS OTA-RC continuous-time filters. 27:993-1001. 1992
- A 10.7-MHz 68-dB SNR CMOS continuous-time filter with on-chip automatic tuning. 27:1843-1853. 1992
- PROGRAMMABLE SWITCHED-CAPACITOR BUMP EQUALIZER ARCHITECTURE. 25:1035-1039. 1990
- A 25 Gb/s, 4.4 V-Swing, AC-Coupled Ring Modulator-Based WDM Transmitter with Wavelength Stabilization in 65 nm CMOS 2015
- A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator with 67.7 dB SNDR using Time-Domain Quantization and Feedback 2010
- Optical I/O Technology for Tera-Scale Computing 2010
- A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects 2008
- A 1.1 GHz fifth order active-LC butterworth type equalizing filter 2007
- An integrated frequency response characterization system with a digital interface for analog testing 2006
- All-digital TX frequency synthesizer and discrete-time receiver for Bluetooth radio in 130-nm CMOS 2004
- Resonant clocking using distributed parasitic capacitance 2004