A Continuous Time Multi-Bit $Delta Sigma$ ADC Using Time Domain Quantizer and Feedback Element Academic Article

abstract

• A third-order CT ADC that replaces the multi-bit quantizer and feedback DAC by a pulsewidth modulation (PWM) generator and time-to-digital converter (TDC) is implemented in 65 nm CMOS technology. The TDC provides a 50-level binary output code and a time-quantized feedback pulse to the modulator. It is shown that the TDC can achieve 11 bit linearity in time steps without calibration or dynamic element matching. The modulator achieves 68 dB DR in 20 MHz BW, consumes 10.5 mW and occupies 0.15 m2. 2006 IEEE.

authors

• Silva-Martinez, Jose

published proceedings

• IEEE JOURNAL OF SOLID-STATE CIRCUITS

altmetric score

• 3

author list (cited authors)

• Dhanasekaran, V., Gambhir, M., Elsayed, M. M., Sanchez-Sinencio, E., Silva-Martinez, J., Mishra, C., Chen, L., & Pankratz, E. J.

citation count

• 50

complete list of authors

• Dhanasekaran, Vijay||Gambhir, Manisha||Elsayed, Mohamed M||Sanchez-Sinencio, Edgar||Silva-Martinez, Jose||Mishra, Chinmaya||Chen, Lei||Pankratz, Erik J

publication date

• March 2011

publisher

• Institute of Electrical and Electronics Engineers (IEEE)  Publisher

published in

• IEEE Journal of Solid-State Circuits  Journal

keywords

• Adc
• Analog-to-digital Conversion
• Baseband Adc
• Continuous Time
• Deep-submicron Cmos
• Delta-sigma Modulator
• Low Osr
• Nanometric Cmos
• Oversampling
• Tdc
• Time Domain
• Time-to-digital
• Time-to-digital Converter

Digital Object Identifier (DOI)

• 10.1109/JSSC.2010.2099893

start page

• 639

end page

• 650

volume

• 46

issue

• 3

URL

• http://dx.doi.org/10.1109/jssc.2010.2099893