A 25 MHz Bandwidth 5th-Order Continuous-Time Low-Pass Sigma-Delta Modulator with 67.7 dB SNDR using Time-Domain Quantization and Feedback Conference Paper uri icon

abstract

  • This paper introduces a continuous-time low-pass sigma-delta modulator operating with a seven-phase 400 MHz clocking scheme to control time-based processing in the 3-bit two-step quantizer and main digital-to-analog converter (DAC). An on-chip voltage-controlled oscillator and a complementary injection-locked frequency divider are utilized for low-jitter clock signal generation with multiple phases, allowing 3-bit pulse-width modulated feedback with a single-element DAC to avoid performance degradation from unit element mismatch problems associated with conventional multi-bit DACs. Fabricated in a standard 0.18 μm CMOS technology, the 5th-order modulator achieves a peak SNDR of 67.7 dB in 25 MHz bandwidth, consumes 48 mW from a 1.8 V supply, and occupies a die area of 2.6 mm 2 . The modulator has a measured SFDR of 78 dB and in-band IM3 under -72 dB with -2 dBFS two-tone signal power. © 2010 IEEE.

altmetric score

  • 3

author list (cited authors)

  • Lu, C., Onabajo, M., Gadde, V., Lo, Y., Chen, H., Periasamy, V., & Silva-Martinez, J.

citation count

  • 42

publication date

  • September 2010