A 90 nm CMOS 16 Gb/s Transceiver for Optical Interconnects Conference Paper uri icon


  • Interconnect architectures which leverage high-bandwidth optical channels offer a promising solution to address the increasing chip-to-chip I/O bandwidth demands. This paper describes a dense, high-speed, and low-power CMOS optical interconnect transceiver architecture. Vertical-cavity surface-emitting laser (VCSEL) data rate is extended for a given average current and corresponding reliability level with a four-tap current summing FIR transmitter. A low-voltage integrating and double-sampling optical receiver front-end provides adequate sensitivity in a power efficient manner by avoiding linear high-gain elements common in conventional transimpedance-amplifier (TIA) receivers. Clock recovery is performed with a dual-loop architecture which employs baud-rate phase detection and feedback interpolation to achieve reduced power consumption, while high-precision phase spacing is ensured at both the transmitter and receiver through adjustable delay clock buffers. A prototype chip fabricated in 1 V 90 nm CMOS achieves 16 Gb/s operation while consuming 129 mW and occupying 0.105 mm2. 2006 IEEE.

published proceedings

  • IEEE Journal of Solid-State Circuits

altmetric score

  • 3

author list (cited authors)

  • Palermo, S., Emami-Neyestanak, A., & Horowitz, M.

citation count

  • 83

complete list of authors

  • Palermo, Samuel||Emami-Neyestanak, Azita||Horowitz, Mark

publication date

  • May 2008